01.05.2024 | Pełny etat | Honeywell International Inc.And marine equipment. More sustainable travel, safer and more efficient flying and a focus on cutting-edge innovation. Key responsibilities ASIC/FPGA design & verification; Working with HDL languages (SystemVerilog, VHDL, Verilog) Working following FPGA/SOC technologies Microchip, AMD (XILINX), Inter, etc
Zobacz później01.05.2024 | Pełny etat | SwediumglobalOf independent work Experience 3 to 5 years of Industry experience in IC design or a matching Ph.D. is expertise in analog circuit design (concepts, design trade-offs, transistor level understanding and technology),excellent understanding of hardware description languages (veriloga
Zobacz później01.05.2024 | Pełny etat | Eltronic A/SAs well as customers globally. Main Responsibilities Ownership of verification strategies for new IP products. Architecting and implementing advanced verification environments for industry standards as System Verilog. Ensuring high test coverage numbers on our IPs. Establishment of test plans
Zobacz później01.05.2024 | Pełny etat | SwediumglobalVerification Expertise in software-driven verification based on SoC. Develop test cases and test framework. Expert in C programming. Develop verification components using C, System Verilog and UVM. Execute and debug test cases. Knowledge in scripting languages (Python, Perl, Linux Shell scripting etc.) Result
Zobacz później24.04.2024 | Pełny etat | Katowice | Intel GmbHAnd stress test generation, verification infrastructures and verification and/or debug flows Extensive knowledge of Verilog and SystemVerilog and working knowledge of UVM methodology Good
Zobacz później24.04.2024 | Pełny etat | Kraków | SiliconcrDocumentation and application notes. Obligatory skills B.S. in electrical/computer engineering, or related degree. Knowledge of circuit design and systems. Excellent verbal, presentation, and written skills. Experience with Verilog, Matlab, PERL, and/or Python programming languages. Knowledge of ISO26262
Zobacz później24.04.2024 | Pełny etat | Katowice | Intel GmbHAnd stress test generation, verification infrastructures and verification and/or debug flows Extensive knowledge of Verilog and SystemVerilog and working knowledge of UVM methodology Good
Zobacz później24.04.2024 | Pełny etat | Kraków | SiliconcrOscillators), high-speed SerDes circuits and fast differential LVDS data interfaces in various CMOS processes from 3 nm to 180 nm for the customers worldwide. For more information, please visit Main responsibilities Generation and verification of real-number Verilog behavioral models for PLLs/SerDes Design
Zobacz później24.04.2024 | Pełny etat | Benetel LimitedCapture. To this end, knowledge of 5G and ORAN is desirable but not essential Digital frontend design and verification techniques using SystemVerilog/Verilog Implementing functional and code coverage techniques in simulation Implementation of DSP algorithms for FPGA Using Matlab for all aspects of FPGA
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