24.04.2024 | Pełny etat | Kraków | SiliconcrOscillators), high-speed SerDes circuits and fast differential LVDS data interfaces in various CMOS processes from 3 nm to 180 nm for the customers worldwide. For more information, please visit Main responsibilities Generation and verification of real-number Verilog behavioral models for PLLs/SerDes Design
Zobacz później24.04.2024 | Pełny etat | Kraków | SiliconcrDifferential LVDS data interfaces in various CMOS processes from 3 nm to 180 nm for the customers worldwide. Main responsibilities Generation and Verification of Verilog behavioral models for IPs like PLLs/SerDes etc. Verification and/or Design of RTL blocks. Development of scripting infrastructure
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