24.05.2024 | Pełny etat | Warszawa | KRYPTON PolskaWbudowanych w FPGA, tworzeniu oprogramowania dla tych systemów i możesz pochwalić się przynajmniej trzyletnim doświadczeniem z pracy w tym zo dobrze znasz z C/C+, co najmniej w podzbiorze dla systemów doświadczenie w pracy w środowiskach Quartus, Qsys, Model Sim
Zobacz później18.05.2024 | Pełny etat | Kraków | Hitachi EnergyExperience of FPGA/ASIC design & simulation in VHDL/(and/or Verilog) - 5 years for Senior, 5-10 for Senior II Good understanding of synchronous design, time constraining and
Zobacz później01.05.2024 | Pełny etat | Honeywell International Inc.And marine equipment. More sustainable travel, safer and more efficient flying and a focus on cutting-edge innovation. Key responsibilities ASIC/FPGA design & verification; Working with HDL languages (SystemVerilog, VHDL, Verilog) Working following FPGA/SOC technologies Microchip, AMD (XILINX), Inter, etc
Zobacz później01.05.2024 | Pełny etat | SwediumglobalOf independent work Experience 3 to 5 years of Industry experience in IC design or a matching Ph.D. is expertise in analog circuit design (concepts, design trade-offs, transistor level understanding and technology),excellent understanding of hardware description languages (veriloga
Zobacz później01.05.2024 | Pełny etat | Eltronic A/SAs well as customers globally. Main Responsibilities Ownership of verification strategies for new IP products. Architecting and implementing advanced verification environments for industry standards as System Verilog. Ensuring high test coverage numbers on our IPs. Establishment of test plans
Zobacz później24.04.2024 | Pełny etat | Katowice | Intel GmbHAnd stress test generation, verification infrastructures and verification and/or debug flows Extensive knowledge of Verilog and SystemVerilog and working knowledge of UVM methodology Good
Zobacz później24.04.2024 | Pełny etat | Katowice | Eltronic A/SSpecifications for new products Implementation and simple verification of designs in Verilog/System Verilog Establish user manual and for other documentation for design Support our verification team in the thorough verification of our products Assist customers in integration and usage of the products Your
Zobacz później24.04.2024 | Pełny etat | Kraków | SiliconcrOscillators), high-speed SerDes circuits and fast differential LVDS data interfaces in various CMOS processes from 3 nm to 180 nm for the customers worldwide. For more information, please visit Main responsibilities Generation and verification of real-number Verilog behavioral models for PLLs/SerDes Design
Zobacz później24.04.2024 | Pełny etat | Kraków | SiliconcrDifferential LVDS data interfaces in various CMOS processes from 3 nm to 180 nm for the customers worldwide. Main responsibilities Generation and Verification of Verilog behavioral models for IPs like PLLs/SerDes etc. Verification and/or Design of RTL blocks. Development of scripting infrastructure
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